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Front End Design Summit at Cadence

Thu, 2012-11-29 10:25 — Gabe Moretti

Cadence is hosting a Front End Design Summit on Thursday, December 6, 2012. The all day workshop which following the tradition of Silicon Valley will start at 9:30am to give time for everyone to battle the traffic, will end at 5:00pm. The workshop will be held in Building 10 at the Cadence campus, 2655 Seely Avenue in San Jose.

Catapult LP Handles System Level Power Issues

Mon, 2012-07-09 08:38 — Gabe Moretti

A few days before DAC Calypto announced Catapult Low-Power (LP), a high-level synthesis (HLS) tool that adds power as an optimization goal. Since August 2011, when Calypto received Catapult C from Mentor the company has integrated the tool within the ESL flow that includes SLEC, its equivalence checking tool, and now has also integrated a power analysis and evaluation function into the tool renamed simply Catapult.

Calypto Announces Catapult Low-Power High-Level Synthesis

Tue, 2012-05-29 14:51 — Gabe Moretti

Calypto Design Systems, Inc. announced Catapult Low-Power (LP). For those that were wondering why Mentor had given Catapult-C to Calypto, and those who having accepted the transfer were wondering what in the world Calypto would do with it, the answer arrived today in the form of a product announcement.

To begin with it is clear how Catapult-C fits with the original Calypto products. I t is a link between ESL and RTL that is parallel to the SLEC product. But the new release is much more than that. It incorporates some of the SLEC technology as well as some of the PowerPro technology, providing a HLS that is also power aware.

Fast memory Networks Explored In Zuken Blog

Fri, 2012-05-11 11:36 — administrator

In a blog titled: "BGA packages – are you designing your high-speed memory networks in the dark?" Andy Buja explores the problems of designing a memory system using DDR3 controller techniques.

Clearly, the end result of any high-speed memory network is for it to work properly when it’s charged-up. With the ability to front-end load constraints and create skew groups along with the schematic, the circuit engineer expects the perfect eye diagram and hopes for perfect alignment of signals across the entire bus in both the simulation results, and even on the bench test prototype.

Read the entire blog by clicking on the link "ZKEN" on the right of the page.

Springsoft Releases Laker³ And A New Analog Prototyping Tool

Tue, 2012-04-17 09:54 — Gabe Moretti

The Laker custom IC design platform may not be the first layout tool an engineer would name, but it has continued to gain market shares since its introduction and now counts leading semiconductors companies as its customers. SpringSoft, Inc. has made a considerable step toward increasing its market share with the release of its Laker3 custom IC design platform and the new Laker Analog Prototyping tool. The third generation of the Laker product family delivers a complete OpenAccess (OA) environment for analog, mixed-signal, and custom digital design and layout that is optimized for performance and interoperability in 28 and 20-nanometer (nm) flows. Laker customers with current maintenance contracts can upgrade immediately at no charge. The new Laker Analog Prototyping tool is list priced starting at US$80,000 per year for a three-year subscription license.

Overcoming Obstacles to ESL with a Universal Transaction-Level Model

Wed, 2012-04-04 09:28 — administrator

Yossi Veller, Mentor Graphics

The shift toward electronic system level (ESL) design and verification is beginning as the productivity of RTL modeling and verification techniques lag behind the remarkable growth of design complexity. ESL methodologies focus on the architecture of the design, raising the level of abstraction for design, modeling, and validation to the transaction level.
A transaction-level modeling (TLM) platform provides an essential framework within which many of the essential design and verification tasks can be performed. Moreover, there is a growing recognition of the advantages of extending this flow by directly synthesizing high-level abstraction code to hardware implementation; i.e., by using high-level synthesis (HLS).

Synopsys Buys STA Insurance

Mon, 2011-10-10 15:14 — Gabe Moretti

Synopsys’s Prime Time has been the standard for Static Timing Analysis practically since its inception. For years, in spite of the best efforts by competitors it has remained the choice of designers around the world. But in the lwst twelve months or so, it has received very serious competition from Magma’s Tekton. This product sports a new architecture and offers accurate results and very good performance, usually better than what Prime Time can do.

Cadence Acquires Azuro

Tue, 2011-07-12 11:04 — Gabe Moretti

Cadence seems to be implementing its "must have" list in alphabetical order. So after Altos it was Azuro's turn. Will a B company be next? Most people in our industry will agree that clock and power optimizations are important, but what I did not know was that Cadence was doing a poor job at it. And so the company found that some key customers were going to Azuro to purchase what they could not get from Cadence. The solution was obvious: purchase the annoying interloper before a real competitor would.

Cadence Announces "App-driven" System Development Flow

Wed, 2011-05-04 07:39 — Gabe Moretti

The new flow is a direct result of the EDA360 vision published just about one year ago. The document recognizes that systems are designed and developed based on the application they provide, not on the latest capabilities of hardware manufacturing. hardware and software components are chosen given the requirements of the application, and in the majority of cases, the software components demand the majority of the development effort, and thus are responsible for the larger share of the cost.

How to Achieve Power Estimation, Reduction and Verification in Low Power Design at RTL

Tue, 2011-04-19 13:47 — administrator

A new white paper written by Dave Allen and Kiran Vittal of Atrenta

Power dissipation is a major concern in modern day IC design. For wireless electronic appliances, battery life is one of the major influencers of the purchase decision and can be an effective differentiator. Mobile phones, PDAs, digital cameras and personal MP3 players are increasingly being sold on their long battery lives. In wired applications, power consumption determines heat generation which in turn drives packaging costs. If not managed properly, this may have significant impact on the end appliance cost.
The landscape complicates if we also factor increasing component density of ICs, which leads to progressively increasing power density. The challenge is to pack in more while still consuming less and less power. Semiconductor industry projections indicate a 4-6x increase in leakage power for designs today and all available techniques must be applied to meet the goal that average and standby power remain flat as complexity increases.
You can read the entire paper at this location: http://www.atrenta.com/solutions_whitepaper.php