This week both Xilinx and Synopsys introduced new products. Xilinx is growing into a complete system company while Synopsys is benefitting from the acquired technology in hardware emulation to keep the competition in this sector very much alive. Taking advantage of the remote management capabilities built in all the latest computing platform, companies, not just governments, can now take a look at your activity on the web. So quit blaming the NSA alone, commercial reasons are an even bigger motivator to know what you are doing. Prakash Narain CEO of Real Intent released a point-of-view column in occasion of DVCon while Accellera's Day offers a birds-of-a-feather session organized around its Multi Language Working Group.
* The coming week is an important week for EDA. DVCon will focus our attention to Verification issues. March 3rd is Accellera day and you can attend a multi-language bird-of-a-feather. In 2012, the Accellera Board tasked representatives from six electronics companies to define a standard for multi-language verification interoperability. Warren Stapleton, Chair of the Multi-Language Working Group (cleverly shortened to MLWG), will introduce the group, review its charter, and explain the progress of the group in an open forum. I noticed that the agenda plans a break during the session. The break is only 5 minutes long, so better hurry up!
* In her Deeper Dive column, Caroline Hayes, Senior Editor at Chip Design magazine explores security issues. Her conclusion is that Big Brother is no longer suspected of watching you – it’s more likely to be a technology corporation. In response, system level designers have made the security of data and content a prime objective in our connected lives.
* Prakash Narain of Real Intent talking about the upcoming DVCon said: "With the Design and Verification Conference right around the corner, it’s a good time to look at Real Intent’s core expertise – SoC sign-off. Along with the continuing need for verification in different application areas, there’s an ongoing need for smarter reporting – analysis that provides a more expanded and deeper understanding of your intent as a designer. We know you are looking for verification reports that are organized in an easy way for review and design debug, so you’re not left drowning in data from the analysis of CDC, Lint checks, hardware reset and initialization, and automatic intent verification. All these reports should present the key issues and let you drill down hierarchically. "
* Xilinx has introduced the UltraScale Multi-Processing (MP) Architecture for its Next Generation Zynq UltraScale MPSoCs. Building on the industry success of the Zynq-7000 All Programmable SoCs, the new UltraScale MPSoC architecture extends Xilinx's ASIC-class UltraScale FPGA and 3D IC architecture to enable heterogeneous multi-processing with "the right engines for the right tasks."
* Synopsys has announced the availability of ZeBu Server-3, which it describes as the industry's fastest emulation system. The release also states that: "With its comprehensive debug capabilities, automated software and tight integration with leading verification and system level tool flows, ZeBu Server-3 delivers a highly productive environment for complex SoC verification. It provides multiple verification use modes, including power-aware emulation, simulation acceleration, in-circuit emulation, synthesizable testbench, transaction-based verification (TBV) and hybrid emulation for deployment flexibility based on project requirements. Because of its small footprint, low weight, modest power/cooling requirements and high reliability, ZeBu Server-3 offers lower total cost of ownership of any commercial emulator. ZeBu Server-3 offers the industry's largest design capacity, supporting chips as big as three billion gates with a highly scalable architecture based on high-density 28-nanometer (nm) FPGA technology."