A typical week in EDA. Speculations about IBM, another Synopsys acquisition, Google continues to diversify, TI gets more modern, Verific does what small companies are supposed to do, that is support standards, and Chip Design covers wearable technology. But it is IBM and Google that add spice to the news this week, or at least rumors about them.
* Sooner or later it had to happen. In Google job posting one reads: "Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing." The complete story here.
* Texas Instruments reference designs are now all stored in the company Electronic Datasheets repository for easy access to all. TI reference design library encompasses the full TI product range of analog, embedded processor and connectivity products for industrial, automotive, consumer, communications and computing applications, and more. Within the TI Reference Designs, one can download User Guides, Test Data, Product Schematics, BOM, Design and Software Files, and Gerber Files, with Product images. The electronic Datasheets can be found here.
* Reports in EE Times by both Junko Yoshida and Rick Merritt suggest that IBM may be in the process of divesting itself of its chip making division. I am skeptical about this. It is more likely that IBM will change its business model while still retaining the division as a research and fabrication unit. It may in fact lease some of the foundry to third parties, like Globalfoundries or Samsung while retaining thew ability to serve the needs of the US government.
* Synopsys has acquired Target Compiler Technologies that provides software tools to design and program application-specific instruction-set processors (ASIPs). ASIPs complement industry-standard processor architectures by enabling designers to implement their own highly specialized software programmable engines for compute-intensive digital signal and data plane processing.
* Verific Design Automation has announced enhancements to its parser for the IEEE 1801-2013 standard for the design and verification of low-power integrated circuits, also known as Universal Power Format 2.1 (UPF 2.1).
The parser performs syntax and semantic checking, preserves all parameter values and stores the UPF data in a parse tree for easy access. The UPF parser includes Verific’s comprehensive error handler, which maintains complete file, line and column information on UPF descriptions.
The IEEE 1801-2013 UPF 2.1 standard, originally developed by standards organization Accellera, is supported by multiple electronic design automation (EDA) vendors, many of whom are Verific customers. It provides a hardware description language independent way of annotating a design with power intent. It defines how to create supply networks to supply power to each design element using a set of commands.
* In this Deeper View, Caroline Hayes, Senior Editor at Chip Design, looks at what is driving the adoption and direction of both the early adopters in wearable technology, and those looking to explore its potential for less obvious end uses. Read the full article here.