Pat Sheridan, Sr. PMM for Synopsys Platform Architect
Rich Collins, Sr. PMM ARC Processors and Subsystems
In response to my question: "What tools or methods do architects and developers have or should have to define a realistic power budget at the system level?" Pat and Rich offered the following article.
Great question! Low power SoC design is a system design challenge which does not stop at the border between hardware and software. The architect, hardware designer, and software developer all play important roles in setting realistic power budgets and the achieving the right result for the system.
Enabling a system to perform with power efficiency requires the right SoC architecture and perfectly matching power management software. Architects and software developers need to address this need as early as possible in the development cycle, and system-level tools and methods for virtual prototyping are available today to help them accomplish this. With virtual prototyping, realistic system simulation enables them to define the power budgets and power modes for all primary system components and to bring-up the power management infrastructure needed by the rest of the hardware and software team during implementation.
Power-aware Architecture Definition
High-end applications like wireless communications, multi-media, networking, or the emerging micro server/data center market are posing enormous challenges on the SoC design to meet performance, power, and cost requirements. For the SoC architect, it is crucial to understand how design decisions impact power and performance of their SoC architecture in the face of complex and dynamic application workloads. Hardware-software partitioning, power domain definition, and dynamic voltage and frequency scaling cannot be determined in isolation.
Virtual prototyping environments for multicore SoC architecture design use application workload modeling to enable early quantitative analysis of power and performance trade-offs long before software is available, to determine the right power-aware SoC architecture and confirm power budgets. Typical questions that the architect can answer using Platform Architect are:
• How to partition the SoC application into fixed hardware accelerators and software executing on processors, determining the optimal number and type of each CPU, GPU, DSP and accelerator
• How to partition SoC components into a set of power domains to adjust voltage and frequency at runtime in order to save power when components are not needed
• How to confirm the expected performance/power curve for the optimal architecture
Figure 1: Power-aware Architecture Definition
Synopsys Platform Architect uses application workload modeling to enable
early quantitative analysis of power and performance, shown above.
Power-aware Software Development
Power efficiency is a major product differentiator – and a major quality concern for software manager. Power management functions are distributed across firmware, operating system, and application software in a multi-layered framework, serving a wide variety of system components from multicore CPUs to hard-disks, sensors, modems, and lights — each consuming power when activated. Even minor software defects can have a ripple effect which drives the mobile device battery to empty many times faster than expected. A bug in a device driver can prevent an entire server from going into a lower power mode. Bringing up and testing power management software is becoming a major bottleneck in the software development process. Software developers are not getting the necessary information about the consequences of their software changes on power, causing significant impact on the user-experience and software development schedules.
Virtual prototypes for software development are fast, fully functional simulators of complete systems under development executing unmodified production code. Benefits for the software team include early availability, excellent debug visibility, and easy deployment. Software teams can use virtual prototypes to bring-up and test of power management software and enable power-aware software development, including the ability to:
• Quickly reveal fundamental problems such as a faulty regulation of clock and voltages
• Gain visibility for software developers, to make them aware of problems that will cause major changes in power consumption
• Simulate real world scenarios and systematically test corner cases for problems that would otherwise only be revealed in field operation
Figure 2: Power-aware Software Development
Synopsys Virtualizer Development Kits are virtual prototypes that enable early bring-up and test of
the power management software used for dynamic voltage and frequency scaling, shown above.
Power-efficient programmable hardware
In addition to a robust set of prototyping and early analysis tools, meeting tight power budgets requires SoCs to be architected using IP developed specifically to address power management. This library of low-power IP typically includes processing cores (CPUs) as well as accelerators, peripherals, I/O and memory. Many processors address extremely power constrained applications by utilizing built-in features such as architectural clock gating, hardware-controlled halt modes, and software programmable sleep modes. These low power instructions manage both CPU energy consumption and power specific resources at the system level. For example, they can indicate a deep sleep mode to an external power management unit or could be used in a dynamic frequency and voltage scaling implementation by switching off PLLs or dropping voltage levels for logic or memory. Architected hardware modes combined with software programmable functionality gives both SoC designers and software developers the resources to minimize energy consumption within their embedded applications.
Figure 3: Power Efficient Programmable Hardware
Many embedded processors such as Synopsys’ ARC EM4, shown above, have been specifically architected to address power constrained applications through hardware gating features and software programmable power modes.
In summary, system-level tools for power-aware virtual prototyping and power-efficient programmable hardware design are available today, enabling architects and developers to define realistic power budgets for their SoC hardware and software much earlier in the development cycle.