Synopsys ventures into the future with IC Compiler II

IC Compiler II should not come as a surprise to those who have noticed the significant increase in complexity of design and verification in moving from 45 to 30 nm processes. If you, like me, have also defined as "diabolic" the cost and complexity of designing for 20 and 14 nm processes.

What is interesting is the pressure Synopsys may be experiencing from long time customers for a new tool. To the point that the announcement on March 24 is a pre-release announcement. Companies are willing to be official beta testers just for the privilege of using a new tool. Since Synopsys is not discontinuing IC Compiler, it is clear that the market is now definitely divided in two segments. The smaller segment representing high revenue potential is made up by those twenty or so companies that absolutely must use the latest process available. The rest of the market made up of companies that produce mostly consumers' products, can live with less demanding processes.

It is clear to me that even very advanced products may be built using stacked dies and on chip networks thus potentially lessening the pressure to use ultra small geometries that really belong in the X-ray lithography space.

Synopsys' Approach

The company chose a clever approach to the development of IC Compiler II. Any new capability requires a new data model, and thus a new tool infrastructure was built using the existing architecture blueprint but creating a totally new data model. The concept of critical engines: Timer, Optimizer, Hierarchy and Clocking was kept but they were all modernized to the new requirements. The CGPL Placer and the Zroute Routers are, at least for now, the same as in IC Compiler. The reason is simple: they are not the critical part in developing the geography of the IC itself. I chose the word "geography" carefully because I want to underline the need of recognizing functional locality and not just physical placement. Once the network is developed and verified, placing and routing is a relatively easier task, especially if the network is well constructed to begin with.

Initial feedback by the, albeit hand picked, early users is not only positive, but shows an eagerness to push Synopsys further and faster: a good thing for the bottom line of the leading EDA vendor. At DAC we will hear and see more details, I am told.

The cost of the tool development is not cheap, so I wonder whether IC Compiler III will be worth it or if we will see an step improvement in system level architecture that will allow the development of powerful computing systems that anyone will be able to build, let alone afford.