The Blue Pearl Software Suite works with the Xilinx Vivado Design Suite running on Windows platforms. It includes linting, CDC analysis and automatic SDC generation. Its generated SDCs automate the synthesis and place and route phases of FPGA design implementation, and reduce iterations and overall design time. Its Visual Verification Environment makes it easy to use.
Zuken announced the immediate availability of version 14 of CR-5000, its advanced PCB and IC Package design software. The new version offers a number of significant productivity enhancements for greater collaboration in FPGA development and for high-speed design. Many enhancements have also been included in CR-5000 Lightning, Zuken’s leading high-speed design verification tool that enables rapid, accurate results, coupled with first-rate signal integrity, EMC and power integrity analysis.
As electronics designers face increasing pressure to shorten the design cycle, the need for automatic generation of key design data increases. The penalty for missing the market window means financial losses for the company and at times, even the need to abandon that particular market. One of the ways to improve reliability and shorten development time is to increase the robustness of the relationship between RTL developers and place and route engineers. Synthesis is the key step in the process of transforming a RTL representation into a gate level one.
Synopsys, Inc. has released new versions of Synplify Pro and Synplify Premier FPGA synthesis tools. The Synplify 2012.03 products include improved synthesis algorithms that accelerate runtime by up to 30 percent. In addition, the Synplify Premier software is enhanced with a new continue-on-error feature to address FPGA designers' need for fast turnaround time by enabling them to generate a report and fix all errors resulting from missing or incorrect design definitions at the end of the hardware description language (HDL) compilation step rather than incrementally fixing an error and rerunning the compile step. Additionally, the new Synplify Premier software release further automates the process of building high reliability and fault tolerance into an FPGA design using a combination of advanced features including selective triple modular redundancy (TMR), fault-tolerant error correcting code (ECC) memories and Hamming-3 encoding for detection and correction of soft errors.
During Last year's Globalpress conference I was introduced to the Zynq platform from Xilinx. At the time I thought it had terrific potential to provide an FPGA based solution to many types of systems. it provides an efficient framework for software development and integration that can support solutions that use large amount of memory.
Cadence Design Systems, Inc. has announced that the company's virtual platform for the Xilinx Zynq™-7000 Extensible Processing Platform (EPP) is available as a production release. Designed to streamline the embedded software development process, the virtual platform enables simultaneous development of hardware and software before hardware availability, providing significant savings in development costs and time-to-market. The Cadence virtual platform for the Zynq-7000 EPP is available now to customers who are in the Xilinx early access program.
Synopsys announced updates to its Identify and Certify FPGA-based prototyping tools. Algorithm advancements in the latest Certify software release produce up to 30 percent faster FPGA-to-FPGA transmission performance using High-Speed Time Domain Multiplexing (HSTDM), which results in higher overall performance of designs prototyped with Synopsys' HAPS FPGA-based prototyping systems.
On the tail of Mentor’s transfer of Catapult C to Calypto, Synopsys, Inc. announced availability of the latest release of its Synplify Pro and Synplify Premier FPGA synthesis tools.
The company states that the new Synplify tool release enables engineers to build higher reliability into their FPGA designs through a new feature that provides automated creation and preservation of error-correction logic, including safe finite-state machines (FSMs). Additionally, an enhanced interface for the tool allows designers to track progress and analyze synthesis results hierarchically. For ASIC prototypers, support for Synopsys DesignWare Library MacroCell IP has been added, broadening DesignWare IP support and improving compatibility with Design Compiler.
Synopsys, Inc. and Achronix Semiconductor announced a multi-year extension of their OEM agreement for Synopsys FPGA synthesis tools. The agreement continues to make Synopsys' FPGA logic synthesis technology available to Achronix customers by expanding support of Synopsys' Synplify Pro® software to Achronix's latest generation of FPGAs, the 22 nanometer Speedster22i™ FPGA Platform. Achronix intends to deliver a Speedster22i FPGA-optimized version of Synplify Pro FPGA synthesis software to its customers as part of its Achronix CAD Environment (ACE) software package, to provide designers of these devices with high performance synthesis technology.
In a move reminiscent of the style of Carl Icahn, Mentor lowered its costs by exchanging Catapult C with stock of Calypto. In this manner no money exchanged hands and Mentor lowered its development and maintenance costs in the very competitive area of High Level Synthesis (HLS). The move came as a surprise to those involved in the Catapult C project. Simon Block, even a couple of weeks ago had agreed to submit an article about the product for the August issue of Assembling The Future newsletter.