IP Cores

Kilopass Antifuse Non-Volatile Memory IP Successful on TSMC 20nm Process

Kilopass announced that its NVM IP is the first antifuse technology to achieve successful test chips on TSMC’s 20nm process. Analysis of the test chips containing Kilopass NVM IP memory modules validated manufacturability, process control tolerance and cell programming characteristics.

Kilopass XPM IP Provides Non Volatile Memory in IBM 65nm LPE Process

Kilopass Technology Inc. has announced the validation of its anti-fuse XPM (eXtra Permanent Memory) NVM IP as "Ready for IBM Technology" in the IBM 65nm 10LPe (low-power enhanced) process. Kilopass' XPM family provides up to 1Mb of storage capacity for portable device SoCs (System on Chip) that need the lower standby power consumption the IBM 65nm 10LPe process provides. Kilopass has successfully completed 1000 hours of High Temperature Operating Life (HTOL) and 1000 hours of High Temperature Storage Life (HTSL) per JEDEC 47 standard qualification on the IBM 65nm 10LPe process with no failures, thus assuring designers of at least 10 years of operating life for the XPM NVM.

Kilopass’ Next-Generation Gusto-2 Targets Instant-On Mobile Devices

Kilopass Technology announced Gusto-2, its second generation of code storage products, to serve the increasing numbers of new system-on-chip (SoC) designs for instant-on mobile devices. Gusto-2 is available for SoC designs targeted for 2013 Q1 fabrication. It will initially be enabled on the 55nm and 65nm logic processes at IDMs and mainstream pure play foundries with enablement on smaller process nodes following.

Kilopass Close to Quadrupling Memory Capacity for Embedding Non-Volatile Data in SoCs

Kilopass Technology Has described at MemCon in Santa Clara, Calif., its new embedded VCM (Vertical Cross-point Memory) NVM IP bit cell. The new VCM bit cell quadruples the density of today’s anti-fuse NVM IP bit cell. The VCM bit cell will make possible program storage where today’s embedded non-volatile memory (eNVM) technology is cost-prohibitive or unavailable at capacities of 4Mb to 32Mb. It will also enable a higher level of performance more similar to SRAM compared to existing slower eNVM technologies or external flash or EEPROM chips.

Synopsys Announces DesignWare DDR4 Memory Interface IP

Increasing amount of firmware in SoC devices requires bigger and faster memory subsystems. Synopsys announced the expansion of its DesignWare DDR interface IP portfolio to include support for next-generation SDRAMs based on the DDR4 standard. By supporting DDR4 as well as DDR3 and LPDDR2/3 in a single core, the DesignWare DDR solution enables designers to interface with either high-performance or low-power SDRAMs in the same system-on-chip (SoC), which is a key requirement of many SoCs such as applications processors for smartphones and tablets.

ARM and Synopsys Expand Collaboration

Just after Synopsys acquired Virage Logic a few companies declared that the purchase would put Synopsys in direct competition with ARM and thus that the account was ripe for the taking. Any intelligent industry analyst, there might be a few remaining, would have immediately seen that the ARC core is not a direct competitor of the ARM family of products. But anything is a good source of rumor, and an opportunity to generate words that enable advertising revenue. Before I go on, I must confess that I am a bit puzzled by the lukewarm efforts made by Synopsys in inserting marketing and sales strength in the ARC product, but then again this is probably one reason that Aart chose Chi-Foon and not me as a co-CEO.

Synopsys Launches Community Site For Users of Verification IP

Synopsys, Inc. announced the launch of VIP-Central.org, the first industry-wide, technical community site focused on system-on-chip (SoC) verification engineers and users of verification IP (VIP). It provides a centralized online resource of relevant forums and blogs focusing on verification of today's industry-standard protocols. Visit VIP-Central.org online at http://www.vip-central.org/.

Kilopass Expands XPM Non-Volatile Memory IP Enablement for Power Management

Kilopass Technology, Inc. announced that it has successfully expanded enablement of its XPM (eXtra Permanent Memory) NVM IP on the Dongbu HiTek AN180 and BD180 BCD (Bipolar-CMOS-DMOS) processes.

Kilopass has also begun enablement of its XPM solutions at additional 180nm BCD foundries due to customer demand. Power management designs targeting mobile devices, hard drives, and the wide range of electronic systems being designed into automobiles, smart cities, and homes are driving increased demand for JEDEC-qualified Kilopass embedded NVM IP to store analog trim, product configuration data, and code storage in BCD process technology.

Kilopass XPM Memory IP Adds Programmability to Javelin Products

Javelin Semiconductor has selected the XPM (eXtra Permanent Memory) Non Volatile Memory (NVM) Intellectual Property (IP) core from Kilopass for its latest product development. Innovator of the world’s first high-performance CMOS 3G power amplifier (PA), Javelin Semiconductor plans to incorporate Kilopass’ NVM IP into next-generation products that include the MIPI RFFE digital interface and support programmable capabilities.

Atrenta Accelerates Growth in Front End Design with Acquisition of NextOp Software, Inc

Atrenta Inc. has acquired NextOp Software, Inc., a provider of assertion synthesis technology. Atrenta's products focus on improving efficiency and reducing cost for the design of complex semiconductor IP and system-on-chip (SoC) devices while NextOp's products focus on improving efficiency and reducing cost for the functional verification of IPs and SoCs. The combination of both company's products creates a more complete SoC Realization platform. NextOp's staff based in Santa Clara will move into the Atrenta San Jose facility. On the other hand, the NextOp's Shanghai facility will become the Atrenta office in China. Financial terms of the transaction were not disclosed.