|PathFinder™: A Dynamic and Static Analysis Solution for IP and Full-chip ESD Integrity ||This paper describes how PathFinder helps designers meet ESD guidelines and identify "weak" areas of the design (layout or circuit) most vulnerable to ESD failures. It also demonstrates how PathFinder can be used for early prototyping and design exploration, especially when clamp cells are inserted inside the core region of the chip.|
|Power and Signal Line Electromigration Design and Reliability Validation Challenges||This paper describes EM integrity analysis for power and signal lines. It outlines the various process and design trends that are increasing the likelihood of EM induced failures in a design and looks at conventional verification techniques for EM integrity and contrasts those with what is required for advanced process nodes.|
|Power Noise Integrity for Analog/Mixed-Signal Designs ||This paper describes the need for power noise integrity solution for analog / mixed-signal designs and the benefits of the Totem platform, its usage model in a design flow, and results from simulation and correlation measurements.|
|RTL Design for Power Methodology||This white paper presents a Design for Power (DFP) methodology, beginning early in the design process at the Register Transfer Level (RTL) for maximum impact on power.|
|Apache Design Automation Chip Power Model (CPM™)||The traditional approach to chip-package-system (CPS) co-analysis and co-optimization lacks the required accuracy and thus limits productivity. To meet the increasing demands for system cost reduction calls for a new methodology that is more comprehensive. This white paper outlines the Chip Power Model (CPM™) technologies and solutions available from Apache Design Solutions to help address the CPS convergence challenge.|
|Do Your Chip a Favor: Manage the Constraints||A design goes through several transformations in a typical register transfer level (RTL) to layout flow, and a variety of verification techniques are employed (simulation, equivalence checking, etc.) to ensure that its intent has not changed. Figure 1 illustrates the overall flow. It’s normal for timing constraints to be created and refined in parallel with the RTL and netlist throughout the design cycle, but these constraints typically don’t undergo the same level of verification (or indeed any verification) before being used. The creation and refinement of constraints is largely a manual, error-prone and time-consuming process, and managing thousands of lines of timing constraints throughout the flow is nearly impossible. Subsequently, constraint problems pose a serious risk to the success of the implementation process.|
|Verification of multi-clock designs||Yesterday's SoCs are today's blocks and sub-chips. The resultant combination of interfaces, protocols and performance objectives regularly results in many clock domains on a single chip. Often, this is further complicated by multiple modes of operation and the associated range of clocking scenarios. This leads to ever increasing numbers of clock interfaces, where data is transferred between clocks of different frequencies and often between asynchronous domains. In this environment, designers, chip integrators and back end engineers must ensure the integrity of the clock architecture, and the integrity of its associated timing constraints.|
|SpyGlassŽ-CDC: Combining Structural and Functional Verification Techniques to Improve Effective Clock Domain Crossing Verification||Multiple, independent clocks are quintessential in SoCs and other complex ASICs today. In some cases, such as in large communications processors, clock domains may number in the hundreds. Clock domain crossings pose a growing challenge to chip designers, and constitute a major source of design errors--errors that can easily slip past conventional verification tools and make their way into silicon.|
|GuideWareT||Advances in silicon technology have enabled unprecedented levels of integration in today's SoC designs. These designs are developed through integration of various sub-systems. After the architecture and top level micro-architecture are reasonably complete, the task of developing and integrating sub-systems begins. These sub-systems may be developed ground-up with brand new sub-system RTL. Additionally, many of the sub-systems can be sourced as IPs from third parties or from an internal library of legacy designs. Integration of these sub-systems begins at appropriate times in the work-flow.|
|Constraints Management: Approaches and techniques for preserving the intent of timing constraints throughout the design flow||As the complexity of designs has scaled, the need to provide accurate physical constraints like timing, area, power and port locations has become increasingly important. Of these, timing constraints are the most difficult to provide since they depend on many external factors like floor planning, routing and integration with other blocks. Properly created timing constraints not only reduce the total effort to achieve timing closure, but also reduce the number of iterations to achieve that goal. These constraints undergo several refinements as they are pushed through the design flow from RTL to post layout. This requires that constraints be managed at each step and properly handed off to the next step to ensure that design intent is preserved. If constraints are not managed properly, unnecessary iterations between front-end and back-end groups occur, and the time to market and end unit cost is impacted.|
|SoC Physical Closure Begins at RTL||By Ramesh Dewangan, Ravi Varadarajan, Jitendra Kumar Gupta, Navneet Mohindru, Satish Soman, Atrenta|
Any survey of chip design teams consistently points to two problem areas impacting quality and schedule of today’s SoCs. Those areas are: a) completeness of verification, and b) physical design closure for area, timing and power for complex IP’s and SoC’s. With the advent of deep sub-micron technology, these problem areas have become exacerbated. In this White Paper, we take a closer look at the physical design closure aspects of advanced SoCs. We provide a root cause analysis of unpredictable physical design closure issues and explore possible solutions and methodologies to address these problems.
|Facilitating At-Speed Test At The Register Transfer Level||This white paper demonstrates a solution for facilitating at-speed test at the register-transfer level. The RTL approach is important, because designers and test engineers usually verify the test coverage only at the gate level during the final ATPG stage. This RTL solution thus saves weeks of effort by fixing potential issues up front.|
The SpyGlass DFT DSM solution is the industry’s first tool which will accelerate design turnaround times by identifying timing closure issues caused by at-speed testing – early at RTL. It provides accurate RTL fault coverage estimation for transition delay testing, together with diagnostics for low fault coverage, early in the design flow, to achieve high test quality with minimum design iterations.
|Congestion Mitigation During RTL Development||Early physical design closure is critical for successful SoC delivery. Routing congestion is one of the key aspects of physical design closure. In this paper we have focused on the logical congestion aspects. We have established the need for a solution geared towards RTL authoring and creation teams.|
|Mr. NAND's Wild Ride: Warning — Surprises Ahead! ||NAND Flash manufacturing cost reductions of 60% per year sustained over nearly a decade have driven many technology changes, developments, compromises, and innovations. Prices have fallen even faster over the past five years, but the precipitous price decline could easily slow due to technical forces and in all likelihood, they will. Further, NAND Flash specifications are changing and will continue to change in predictable and unpredictable ways due to these forces. These changes are taking place throughout the industry, not with just one manufacturer's NAND Flash devices. These changes will create new capabilities for NAND users, will impose extra performance burdens, and may ultimately limit the flexibility of NAND Flash in future device generations compared to what is available today.|
|Anticipate AMBA 4 SoC Design and Verification Challenges ||ARM's series of AMBA specifications have become the de facto standard for SoC (system-on-chip) interconnects since ARM introduced the first version of the specification more than 15 years ago. ARM introduced the latest version of the specification, AMBA 4, in March 2010. AMBA 4 is actually a collection of specifications (including AXI4, AXI4-Lite, and AXI4-Streaming), which may well revolutionize the future of high-performance SoC interconnects.|
Based on the industry's needs, AMBA 4 resulted from a collaborative effort by more than 35 of the industry’s leading OEM, semiconductor, EDA, and IP vendors. The AMBA 4 protocol is available now. It directly addresses the needs of high-performance, low-latency, and low-power designs.
|Post-Silicon Validation Using Formal Analysis ||Verifying the current generation of complex SoCs requires the best methodology and tools, including the application of high-capacity formal verification technologies throughout the design flow, from architectural exploration to post-silicon debug. We see this last area, post-silicon debug, as an important value delivered by formal technology for design and verification teams who have not employed formal earlier in the process to get the design right the first time. As the case studies presented in this white paper demonstrate, the use of formal to find, fix, and verify the fix adds tremendous value in the post-silicon lab.|
|Using Formal Verification Across a Spectrum of Design Applications||Chip designers worldwide have told us that Jasper is fundamentally different in how we approach their technical and business problems by delivering a high ROI (return on investment) through the application of advanced formal verification techniques. Our tools address a spectrum of key verification challenges - from getting the architecture unambiguously right, to putting more power in the hands of designers, to promoting design reuse, to verifying critical functionality, to reducing process bottleneck, and even silicon debug.|
|Boosting Designer Productivity by Using Look-ahead Constraint Analysis Technology ||Timing constraints are a crucial specification in the modern integrated circuit (IC) design flow. Implementation and signoff tools rely on them at almost every step of the design process. The rapid increase in design size and complexity, as well as the widespread reuse of intellectual property (IP) design blocks, has led to a major increase in both the extent and the complexity of timing constraints specification. Ensuring high-quality timing constraints is paramount to efficient design implementation, especially during handoffs between teams. Incomplete, inconsistent, or conflicting constraints can cause optimization and implementation tools to run ineffectively or to never converge.|
In this paper, we present a unique constraint analysis technology that checks for timing constraints problems and provides an interactive environment with context-sensitive diagnostic and fixing suggestions. Using this technology, design teams can save several weeks of engineering effort in a typical IC design project.
|StarRC Custom Rapid3D Extraction ||Accurate parasitic extraction is critical to the success of today’s system-on-chip (SoC) designs because of the growing use of sensitive custom circuits and the vulnerability of layout to increased process variation and parasitic effects. The nanometer SoC designers need a highly accurate three-dimensional (3D) field solver to extract larger proportions of the designs to ensure silicon success. A high-performance and high capacity field solver that is integrated with their existing post-layout extraction and simulation flow will enable designers to achieve their accuracy criteria with confidence as well as successfully meet their tight tape-out schedules. The next-generation Rapid3D technology in StarRC Custom provides an integrated 3D extraction solution to address these growing accuracy, performance, capacity and ease-of-use needs. This paper presents the new Rapid3D technology and the benefits it provides for a range of target applications, including IP characterization as well as custom analog/mixed-signal (AMS), high-speed digital and memory array designs.|
|Benefits of Using ESP in Memory Designs ||ESP is an equivalence checking tool commonly used for full functional verification of custom designs such as memories, custom macros, standard cell, and IO cell libraries. It is used to ensure that two design representations are functionally equivalent. Many people are familiar with the logic cone based equivalence checking which is very effective for synthesizable designs with gate-level implementations, but it cannot be easily adapted to full custom circuits like memories and custom macros. ESP, using formal technique, is based on symbolic simulation to remove many of the restrictions that are imposed by the logic cone based equivalence checking.|
|StarRC™ Custom: Next-Generation Modeling and Extraction Solution for Custom IC Designs ||IC design is facing significant challenges beyond the 40-nm process technology node because of increased process variation and its impact on circuit behavior and performance. At advanced process nodes, the increasing number of layers and new device structures result in hundreds of new parameters and many new parasitic effects, which require higher levels of accuracy in modeling and parasitic extraction for simulation and signoff analysis. Custom digital, analog/mixed-signal, and memory designs are particularly sensitive to the nanometer device parameters and parasitics. At 40-nm process technology and beyond, approximating or ignoring the new interconnect and device effects in custom designs can lead to inaccurate post-layout simulation results and jeopardize the chances of successful silicon. The Synopsys StarRC™ Custom extraction solution offers a wide range of features including advanced interconnect and device parasitic modeling and extraction that enable increased signoff accuracy and productivity for today’s system-on-chip (SoC) custom IC designs.|
|In-Design Rail Analysis™ Accelerates Power Network Closure ||In today’s complex system-on-chip (SoC) designs, static and dynamic voltage-drop and electromigration (EM) effects are increasing. At 90 nanometer (nm) and below, these effects are having a profound impact on timing, contributing 10 to 15 percent delay sensitivity and overall design viability. Due to the performance sensitivity to power and ground (P/G) noises, rail analysis solutions that have been used in high performance networking, wireless/mobile or low-power consumer applications become critical for all design applications at advanced process nodes. These applications are facing challenges of increasing power network failures that are resulted from the increased power and current densities, technology and voltage scaling, larger die sizes, higher variance, and so on.|
With the increasing demands on rail analysis solutions and the complexity of the designs, the existing rail analysis solutions of checking designs upfront or at the tape-out stage are no longer sufficient. IC designers need a rail analysis solution that can easily analyze and optimize power and ground (P/G) network at any stage in the implementation flow. The solution needs to be easy to use, requires minimal setup, and provides intuitive graphical user interface for debugging, fixing, and refining. Most of all, the solution has to fit with their existing implementation flow and yet offers comprehensive P/G grid analysis.
|PrimeTime Advanced OCV Technology ||An accepted trend in the semiconductor industry, where process geometry is continuously shrinking, is the growing impact of variation in static timing analysis (STA). Similar to Signal Integrity (SI), which was introduced as a first order effect in 130-nm and then became more sophisticated over geometry nodes, on-chip-variation (OCV) started at 130-nm and its effects are increasing with shrinking geometry nodes. A preliminary solution to account for OCV was to apply a flat global margin across the entire chip. However, the growing impact of variation in modern designs requires an improved OCV handling capability that takes advantage of improved device-level variation techniques.|
|High-Level Synthesis: C / C++ for Complex Hardware Design ||Over the years, the semiconductor industry has been using C/C++ high-level synthesis (HLS) tools as one way to address the complexity of implementation and verification of hardware acceleration cores due to the growing complexity of standards in video, imaging, wireless, and other multimedia and communications applications. However, these challenges have limited the adoption and scalability of these tools. This paper will discuss some of these challenges and introduce Synphony C Compiler (SCC), a new high-level synthesis product from Synopsys that includes some unique and effective technologies that address the challenges in high-level synthesis adoption.|