Mark Gogolewski CFO and CTO of Denali Software described the flow they used to verify the latest PCI-x IP in his talk "Beyond Endless Verification: Delivering High Quality at Low Expense". Everyone faces the challenges imposed on designs by extensive verification, and want to achieve two seemingly incompatible goals; higher quality and lower costs.

Use and reuse of IP is becoming one of the keys to improving designer productivity for the very large SoCs. Large function blocks are becoming the next level of abstraction in design. Industry-wide, the problem is that the time to verify and test a design is rapidly approaching or exceeding 70 percent of the total hardware design cost and time. This trend is neither affordable nor sustainable and forces schedules to fall rapidly out of control.

Gogolewski described his company's efforts to verify a PCI express design. This is a component that has specifications that are of greater complexity than much larger designs. In addition to requiring hundreds of pages to define the specifications, these specs are also constantly changing. The latest version has 75 options just for configuration, 1600 input parameters, 150,000 lines of code, and uses over one million gates. To verify the design, Denali moved to a minimum size team that used lean design methods for the verification. To minimize process overhead, they established clear goals and targets for the verification team which resulted in a flow similar to the AGILE process used in software.

In comparison, most large companies use a waterfall flow where the verification progresses from the top down to increasing refinement and resolution. This flow is accompanied by a many-layered bureaucracy that gauges performance and completion on ill-defined metrics. This flow may be appropriate for very large scale projects with large design teams and lengthy schedules if well managed. But the method is challenged when the design is in a state of flux and has many changes, and is also always very costly.

In designs like the PCI express, change is inevitable. The verification team had to address newly required changes in specifications, changes due to customer inputs, and also had to address changes associated with fixing problems in the design. The first task was to develop a clear user guide and define all the configuration variables and develop an unambiguous source document. This was not an easy task because the design configuration space is highly multidimensional.

The test bench architecture was based on SystemVerilog but any other assertion-based verification language could also have been chosen. They created a summary of all the features and define the interface sequences so they could test all the signals based on a bus functional model and monitor test points. In addition to their own development, they also adopted existing verification IP for standard PCI functions.

The configuration test plan is feature based and convergence driven. They defined limits to convergence groups and convergence points, and defined and measured quality along the way. For standard interface products, configuration testing is important. Testing included multi-configuration regression suites as well as random and scattered test selection. They tracked errors in a database to measure bug detection and correction rates as well as to identify areas requiring more intense scrutiny.

The combination of a focused verification team, the reuse of existing verification IP, data-driven metrics, and minimal management overhead resulted in a reduction of total verification time to 43 percent for the total development. This is significantly lower than the 70 percent of design time attributed to other verification flows of similar magnitude. With further refinement, it may be possible to reduce verification time to as little as 35 percent of total design effort with this design flow.