In a blog titled: "BGA packages – are you designing your high-speed memory networks in the dark?" Andy Buja explores the problems of designing a memory system using DDR3 controller techniques.

Clearly, the end result of any high-speed memory network is for it to work properly when it’s charged-up. With the ability to front-end load constraints and create skew groups along with the schematic, the circuit engineer expects the perfect eye diagram and hopes for perfect alignment of signals across the entire bus in both the simulation results, and even on the bench test prototype.

Read the entire blog by clicking on the link "ZKEN" on the right of the page.