Mentor Graphics Contributions to TSMC's 20nm Design Infrastructure

During the last few days, I have received a number of press releases from both Cadence and Synopsys dealing with their work with TSMC on the 20 nm process. It then makes sense for me to hear from Mentor Graphics as well. Their news, unlike their two direct competitors, did not specifically focus on 3D-IC technology, although a tweet from Dennis Brophy chirped about it, but instead deals with a broad range of tools.

Physical Design

Olympus-SoC has a comprehensive feature set to support the 20nm flow requirements including DRC/DP-aware routing, litho pattern matching, fixing and timing closure, coloring aware pin access, critical net routing, and DP-aware placement. The tool also provides database support for DP and pre-coloring, post-route dynamic power optimization, intelligent gate sizing and Vt assignment, voltage-dependent design spacing rules, in-chip overlay (ICOVL), dummy typical critical dimension (DTCD) and boundary cell insertion.

For custom and analog designs, the Pyxis IC Station solution provides a complete custom design flow from design capture through floor planning, polygon editing, physical layout, schematic-driven layout, chip assembly and interactive custom routing. Based on TSMC 20nm requirements, a new sensitivity analysis feature is implemented to work in conjunction with the Eldo fast SPICE simulation products, and voltage-dependent design rule checking (DRC) works seamlessly with Calibre nmDRC, Calibre nmLVS and Calibre RealTime products.

Physical Verification

The Calibre nmDRC platform has a new engine to support DP anchoring and pre-coloring, DP design rule checking, voltage-dependent checking and patented real-time graphical “error rings” for coloring conflict resolution to reduce time consuming iterations when fixing DP violations.

Mentor and TSMC collaborated on a circuit verification solution for 20nm that addresses potential reliability issues such as electrostatic discharge (ESD) and latch-up. The Calibre PERC product checks for potential sources of electrical failure, including checks that TSMC has advocated but have not been addressed by other EDA tools. It provides a powerful environment for debugging problems with an integrated view of circuit connectivity, topology, physical layout and design rules that is not available in any other tool, and is fully scalable to handle full-chip signoff of the largest designs.

Another innovation in the Mentor 20nm reference flow for TSMC is the Calibre SmartFill solution, which optimizes filling techniques to reduce the risk of differences between pre- and post-fill timing analysis, while ensuring that overall run times and files sizes are controlled despite the significant increase in GDS data at 20nm. The flow also incorporates the Calibre LFD product working with the TSMC Unified DFM Engine, which incorporates Calibre Pattern Matching technology to accelerate the litho hot spot detection at 20nm.

The Calibre RealTime product, which provides immediate design rule checking and fixing guidance during custom layout editing, has been extended to support full sign-off verification of 20nm rules, including DP checking and debugging aids, and voltage-dependent checks. Calibre RealTime brings signoff verification into the design creation process, providing dynamic feedback to layout engineers as they create and edit the layout. It also helps users create compact and optimized layout when designing with multiple supply voltages. Calibre RealTime is interoperable with the Mentor Pyxis IC Station, Mentor DESIGNrev, and SpringSoft (now Synopsys) Laker layout tools.


The Calibre xACT 3D tool provides reference-level (field solver) extraction accuracy with fast turnaround to address new complexities such as unavoidable misalignment of layout masks associated with double patterning (DPT). The Calibre xACT 3D product is able to interoperate with the customer’s layout design environment through TSMC-defined application protocol interface.

Silicon Test

The Tessent silicon test product suite for 20nm provides user-defined fault models and cell-aware test pattern generation, which allows test engineers to improve the coverage and quality of IC test. Cell-aware testing detects bridging and open defects internal to cells, which are undetected by conventional fault models that only test the cell periphery and interconnections. The Tessent TestKompress product generates patterns to specifically target these additional defects, providing higher confidence in production testing with minimal impact to test time.