Synopsys and TSMC Deliver 3D-IC Design Support

May be you think the 3D-IC pace of development is too slow, but I am of the opposite point of view. Synopsys announced that it is delivering a comprehensive 3D-IC design solution that is included in TSMC's CoWoS™ (Chip on Wafer on Substrate) Reference Flow.

The design flow is the result of the latest collaboration between the companies on 3D-IC integration technologies. It provides a smooth transition from a traditional "2D" integrated circuit (IC) to a multi-die stacking design flow. In support of the TSMC CoWoS reference flow, Synopsys has released enhanced versions of its Galaxy Implementation Platform tools for physical implementation, parasitic extraction, physical verification and timing analysis With the new flow and tool enhancements, engineers can increase productivity, shorten time-to-market and speed time-to-volume when designing multi-die systems for TSMC CoWoS silicon.

Synopsys' Galaxy Implementation Platform features support for TSMC's CoWoS reference flow and technology. TSMC has validated Synopsys' implementation, analysis and signoff tools, including:

Physical Implementation
• IC Compiler™ multi-die physical implementation with support for placement, assignment and routing of microbump, thru-silicon via (TSV), probe-pad and C4; combo bump cells allowing simplified and flexible bump assignment; microbump alignment checks; redistribution layer (RDL) and signal routing, and power mesh creation on CoWoS interconnection layers.

Analysis and Signoff
• Hercules layout vs. schematic (LVS) connectivity checking between stacked die
• StarRC™ Ultra parasitic extraction support for TSV, microbump, RDL and signal routing metal for CoWoS design interconnection
• PrimeTime® timing analysis of multi-die systems

Synopsys' 3D-IC solution is currently in limited customer availability. For more information on the Synopsys 3D-IC solution, please visit this site.