Synopsys Announces DesignWare DDR4 Memory Interface IP

Increasing amount of firmware in SoC devices requires bigger and faster memory subsystems. Synopsys announced the expansion of its DesignWare DDR interface IP portfolio to include support for next-generation SDRAMs based on the DDR4 standard. By supporting DDR4 as well as DDR3 and LPDDR2/3 in a single core, the DesignWare DDR solution enables designers to interface with either high-performance or low-power SDRAMs in the same system-on-chip (SoC), which is a key requirement of many SoCs such as applications processors for smartphones and tablets.

Synopsys' DesignWare DDR4 IP solution consists of the DDR4 multiPHY and Enhanced Universal DDR Memory Controller (uMCTL2) that connect through a commonly used DFI 3.1 interface. The new DDR4 IP supports all key DDR4 features planned for the upcoming JEDEC standard and, compared to the previous version, includes a 13 percent increase in raw bandwidth, up to a 50 percent reduction in overall latency and new low-power features that provide intelligent system monitoring and control to power down elements of the IP as determined by the system's traffic patterns. Real-time scheduling features in Synopsys' unique CAM-based DDR controller can optimize the scheduling of data read/write traffic from multiple hosts, maximizing performance and minimizing latency.

Availability for the DesignWare DDR4 multiPHY and Enhanced Universal DDR Memory Controller (uMCTL2) with support for DDR4 is planned for Q4 2012.