I received an email from Ry Schwark of Mentor about the suit they filed against EVE. The relatively short email gives some additional news about the background.

Ry states that:

"Mentor has over 100 patents issued and 40 more pending on emulation technologies. These patents represent a significant investment from the company and an important asset of our shareholders. We have an obligation to defend that intellectual property and to receive fair value for it." It is true that the company has a fiduciary responsibility to protect stockholders' investments. Thus if they decided to take action, they must have felt that the value of the company would be diminished unless the patent were protected.

Synopsys, Inc. has launched the DesignWare® USB Software Alliance Program with leading USB software providers emsys, Jungo, MCCI and MicroDigital as inaugural members. This alliance program establishes an ecosystem of qualified USB software providers for drivers, firmware and stacks which have proven interoperability with Synopsys' DesignWare USB 2.0 and SuperSpeed USB 3.0 IP. Synopsys and its DesignWare USB Software Alliance Program members can help designers to quickly incorporate USB connectivity into their system-on-chips (SoCs) with less risk and provide consumers with the plug-and-play functionality required for PCs, peripherals, mobile devices and consumer electronic products.

Synopsys, Inc. announced the availability of the Time Division Duplex (TDD) mode in its Long-term Evolution (LTE) Model Library for physical layer system simulation. The addition of the TDD mode to the proven LTE Model Library enables developers of semiconductors for LTE network equipment and devices to quickly and reliably extend their designs to support this important version of the 3rd Generation Partnership Project (3GPP) LTE standard.

Synopsys, Inc. and Lattice Semiconductor Corporation announced a multi-year extension of Lattice's OEM agreement for the Synopsys Synplify® FPGA synthesis tools, which Lattice has been offering to its customers for more than 10 years. Under the terms of the agreement, Lattice Semiconductor will provide specific versions of Synopsys' Synplify Pro® and Synplify® software as part of its programmable logic design environments, including the recently announced Lattice Diamond™ FPGA design environment. This agreement ensures continued high-quality, reliable and fast logic synthesis solutions for designers targeting Lattice CPLD and FPGA products.

Synopsys, Inc. announced that TSMC has successfully taped out a complex 28-nanometer (nm) Product Qualification Vehicle (PQV) test chip using Synopsys' Galaxy™ Implementation Platform. Key features used to design the PQV test chip include 28-nm design rule support for place-and-route, interconnect process modeling, IEEE 1801-2009 (UPF)-based hierarchical low power flow, power-aware design-for-test (DFT) and advanced signoff capabilities. Synopsys tools exercised by TSMC in the RTL-to-GDSII implementation and signoff flow for this test chip development included DC Ultra™ RTL synthesis, IC Compiler physical implementation, PrimeTime® SI timing signoff and StarRC™ Ultra parasitic extraction.

Aldec has announced ALINT™ 2010.06. The release introduces a new methodology, phase-based linting (PBL), which provides structured and prioritized phases for the analysis of HDL design issues, significantly improving development productivity and overall efficiency.

Magma Design Automation Inc. announced that TSMC used Quartz™ DRC for physical verification of its 28-nanometer (nm) product qualification vehicle (PQV) test chip. PQVs are representative of design data customers will use in production designs. By designing and manufacturing the PQV test chip, TSMC offers its customers greater confidence in achieving silicon success in its 28-nm processes.

Cadence Design Systems, Inc. announced today that it will align product development to deliver on the EDA360 vision. The company will line up research and development (R&D) around the three core tenets of the vision: System Realization, SoC Realization, and Silicon Realization.

Synopsys, Inc. has announced that Creative Chips, a mixed-signal semiconductor IC provider, has taped out its most complex mixed-signal chip to date using Synopsys' Galaxy™ Implementation Platform. The 180-nanometer (nm) CMOS industrial bus controller contains complex analog and digital blocks that were created using the Galaxy cell-based physical implementation solution and Synopsys' Galaxy Custom Designer® custom implementation solution as a unified platform to accelerate time-to-market. The Custom Designer solution was also used for full-chip editing and final chip-finishing tasks. Using this unified solution enabled Creative Chips to meet its aggressive schedule and die-size requirements.

Apache Design Solutions, the technology leader in power integrity and noise closure for chip-package-systems (CPS) convergence, today announced that the company has achieved record bookings and revenue in Q2, while maintaining profitability. Growth in Q2 came from increased adoption of Apache’s products - PowerArtist™, RedHawk™, Totem™, and Sentinel™ - by multiple new customers across broad market segments. In addition, AMD chose Apache as their global supplier for power, noise, and reliability sign-off solution. The company also achieved 100% renewal from existing customers.