The pressure to improve the verificat5ion environment is growing. Very large designs enabled by continuous advances in semiconductors manufacturing as well as the acceptance of third party IP use has increased the difficulties faced by verification engineers. Recent product releases in the emulation and acceleration market, in particular from Mentor, and virtual prototyping from Synopsys, point to increased attention on the part of EDA vendors to this market.
Cadence Design Systems, Inc is announcing a new in-circuit acceleration based on the Incisive and Palladium XP platforms for the company’s System Development Suite, extensions to the Verification IP Catalog for acceleration and emulation, and new IP targeting full system design and verification to give engineers the ability to go beyond simulation to speed verification of large-scale SoCs, sub-systems and systems.
When Calypto first introduced its first functional verification product using a proprietary Sequential Equivalence Checking algorithm it likely did not have any idea of the breath of products it now markets. Since then SLEC has grown significantly in capacity and it now exists in four different products, each optimized for a specific purpose.
In a commentary dated May 9th in EE Life that you can read at http://bit.ly/KbmGUc Andre Hassan of Kilopass casts serious doubts about the viability of 3-D packaging. The article looks at the practical obstacles in matching a memory die produced by a supplier with a logic die produced by a different one. Without a doubt the author has a point. Too often, especially from EDA vendors, we hear that the industry is moving rapidly toward 3-D and that the acceptance of the method depends only on design technology and, of course, the expensive tools that go with it.
In a blog titled: "BGA packages – are you designing your high-speed memory networks in the dark?" Andy Buja explores the problems of designing a memory system using DDR3 controller techniques.
Clearly, the end result of any high-speed memory network is for it to work properly when it’s charged-up. With the ability to front-end load constraints and create skew groups along with the schematic, the circuit engineer expects the perfect eye diagram and hopes for perfect alignment of signals across the entire bus in both the simulation results, and even on the bench test prototype.
Read the entire blog by clicking on the link "ZKEN" on the right of the page.
One of the major problems facing EDA companies is how to expand into related markets in order to increase their revenue potential and at the same time lower the risk of being impacted by market fluctuations. Mentor, for example is increasing its investment in embedded software and in discrete systems. Synopsys is choosing the opposite direction and entering the market for semiconductors fabrication. The new acquisition is not the first one, but a way to increase the know-how and provide tools for additional applications.
While attending the Globalpress Summit a couple of weeks ago, I heard Mentor Graphics announcement of the Veloce2 platform, the next-generation of emulation solutions for the verification of electronic system and Systems on Chip (SoC) designs. Built to accommodate up to two billion gate designs, the Veloce2 platform is expected to deliver twice the performance, twice the capacity and four times productivity gain in the same footprint and power consumption as the first-generation Veloce platform.
JasperGold from Jasper Design Automation has been one of the leading formal verification tools practically since the formal verification market was created. About a year ago Oz Levia and Rob van Blommestein joined Jasper to help with marketing. The first new product under their leadership has just been launched. As you would expect it is a bit unconventional and yet quite modern.
This was my third Globalpress Summit and I enjoyed it. This year marked the tenth anniversary of the event. There were a total of 46 editors in attendance, representing 17 countries. Twenty three editors came from 5 Asia countries: China, India, Japan, Korea, and Taiwan. Sixteen came from Europe representing 11 countries including Austria, Denmark, France, Germany, Holland, Hungary, Italy, Norway, Sweden, Switzerland, and the UK. Seven editors from the US completed the audience.
The MIPI Alliance is a global, collaborative organization comprised of companies that span the mobile ecosystem committed to defining and promoting interface specifications for mobile devices. By joining the alliance, EVE will complement its family of fast ZeBu (Zero Bugs) emulation systems with synthesizable emulation verification components supporting MIPI standards.
A little over a month ago, Vaishnav Gorur of Real Intent published an article on Tech Forum with the title "Blindsided by a Glitch".
The article provides good design guidelines while pointing out that following the guidelines is not always sufficient to avoid downstream problems. The article made me think about how dependent on EDA tools some designers can be to the point of allowing such tools to introduce design errors that are justifiable given the algorithms and rules pertaining to such tools.