This site is dedicated to the thoughtful analysis of the EDA industry. It will provide editorial pieces about events in the EDA industry that, in our opinion, are significant to developers of electronic systems. More.

Jim Hogan Emerging Companies Series

Last time I spoke with Jim Hogan, a couple of months ago, he was excited about his investments in companies outside of EDA, clearly signaling that he believed that EDA had reached the end of the loving relationship with the venture capital group.

EVE Expands The Capabilities Of Its Zebu And Unveils 10-Gigabit Ethernet Validation Platform

EVE today announced a variety of new software to expand the capabilities of its ZeBu system-on-chip (SoC) emulation platform, including power-aware verification, post-run debugging, two vertical application validation platforms, low-power and Flash memory models, and electronic system level (ESL) tool interfaces. "Today's emulation platforms have evolved into complex verification environments to address hardware/software integration and embedded software validation of large designs," remarks Luc Burgun, EVE's chief executive officer and president.

Kilopass NVM IP Cores Deliver Footprint and Pin Compatibility

As the use of NVM memories increases significantly, companies need to be assured of reliable second source options. Kilopass now has qualified eight different semiconductors suppliers who can assure footprint and pin compatibility for its devices fabricated at the 130/110 node.

Kilopass Technology Inc allows SoC designers to select any hard IP core-IP supplied as GDSII hard macro-from the entire library of Kilopass XPM (eXtra Permanent Memory) and Gusto NVM IP, drop it into a design for fabrication at any of eight top-tier foundries at the 130/110nm node.

Cadence Expands System and SoC Verification Offerings

The pressure to improve the verificat5ion environment is growing. Very large designs enabled by continuous advances in semiconductors manufacturing as well as the acceptance of third party IP use has increased the difficulties faced by verification engineers. Recent product releases in the emulation and acceleration market, in particular from Mentor, and virtual prototyping from Synopsys, point to increased attention on the part of EDA vendors to this market.

Cadence Design Systems, Inc is announcing a new in-circuit acceleration based on the Incisive and Palladium XP platforms for the company’s System Development Suite, extensions to the Verification IP Catalog for acceleration and emulation, and new IP targeting full system design and verification to give engineers the ability to go beyond simulation to speed verification of large-scale SoCs, sub-systems and systems.

Calypto Enriches Catapult C With the Release of Interface Libraries.

When Calypto first introduced its first functional verification product using a proprietary Sequential Equivalence Checking algorithm it likely did not have any idea of the breath of products it now markets. Since then SLEC has grown significantly in capacity and it now exists in four different products, each optimized for a specific purpose.

Discussion on 3-D Packaging Addresses Costs

In a commentary dated May 9th in EE Life that you can read at Andre Hassan of Kilopass casts serious doubts about the viability of 3-D packaging. The article looks at the practical obstacles in matching a memory die produced by a supplier with a logic die produced by a different one. Without a doubt the author has a point. Too often, especially from EDA vendors, we hear that the industry is moving rapidly toward 3-D and that the acceptance of the method depends only on design technology and, of course, the expensive tools that go with it.

Fast memory Networks Explored In Zuken Blog

In a blog titled: "BGA packages – are you designing your high-speed memory networks in the dark?" Andy Buja explores the problems of designing a memory system using DDR3 controller techniques.

Clearly, the end result of any high-speed memory network is for it to work properly when it’s charged-up. With the ability to front-end load constraints and create skew groups along with the schematic, the circuit engineer expects the perfect eye diagram and hopes for perfect alignment of signals across the entire bus in both the simulation results, and even on the bench test prototype.

Read the entire blog by clicking on the link "ZKEN" on the right of the page.

Synopsys Gets Even Closer To Silicon

One of the major problems facing EDA companies is how to expand into related markets in order to increase their revenue potential and at the same time lower the risk of being impacted by market fluctuations. Mentor, for example is increasing its investment in embedded software and in discrete systems. Synopsys is choosing the opposite direction and entering the market for semiconductors fabrication. The new acquisition is not the first one, but a way to increase the know-how and provide tools for additional applications.

Mentor Improves Emulation With Veloce2 and VirtuaLAB

While attending the Globalpress Summit a couple of weeks ago, I heard Mentor Graphics announcement of the Veloce2 platform, the next-generation of emulation solutions for the verification of electronic system and Systems on Chip (SoC) designs. Built to accommodate up to two billion gate designs, the Veloce2 platform is expected to deliver twice the performance, twice the capacity and four times productivity gain in the same footprint and power consumption as the first-generation Veloce platform.

Formal Verification: There Is An App For That

JasperGold from Jasper Design Automation has been one of the leading formal verification tools practically since the formal verification market was created. About a year ago Oz Levia and Rob van Blommestein joined Jasper to help with marketing. The first new product under their leadership has just been launched. As you would expect it is a bit unconventional and yet quite modern.

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