This site is dedicated to the thoughtful analysis of the EDA industry. It will provide editorial pieces about events in the EDA industry that, in our opinion, are significant to developers of electronic systems. More.

Table Talk on the Emerald Princess

One of the attractions of going on a cruise is meeting people I would otherwise never meet. This last cruise on board of the Emerald Princess offered interesting opportunities. My wife and I always choose late dining because it provides the best opportunity of sharing a table with repeat cruisers that have interesting lives.

This is how I met Mary Lou and Hal. Mary Lou is a very successful marketing and promotion professional that works for a major TV network. She lives in Southern California. Hal is a retired financial analyst who lives in New York City.

Counting Visitors

Once again the world of EDA, well a subset of that world at least, is having fits. This time, and it is not the first time, the cause is an article by John Cooley. John has leaked information he obtained I am told third hand from uncommon channels to continue his private war with Daniel Nenni. You can read it at http://www.deepchip.com/items/0516-07.html.

Real Intent Records Banner Year

During this year, Real Intent evolved from an EDA formal verification company to a verification solution company. In fact, Formal is just one of verification's aspects.

Real Intent Releases New Version of Ascent Lint for Early Functional Verification

Real Intent, Inc. announced version 2.0 of its Ascent Lint tool for early functional verification. It adds 60 comprehensive rules including new FSM checks, while maintaining its analysis speed of up to 450M gates in less than one hour, with no need for hierarchical processing. Real Intent also added Verdi3 support for integration to this industry-leading debug platform from Synopsys.

Kilopass Antifuse Non-Volatile Memory IP Successful on TSMC 20nm Process

Kilopass announced that its NVM IP is the first antifuse technology to achieve successful test chips on TSMC’s 20nm process. Analysis of the test chips containing Kilopass NVM IP memory modules validated manufacturability, process control tolerance and cell programming characteristics.

Kilopass XPM IP Provides Non Volatile Memory in IBM 65nm LPE Process

Kilopass Technology Inc. has announced the validation of its anti-fuse XPM (eXtra Permanent Memory) NVM IP as "Ready for IBM Technology" in the IBM 65nm 10LPe (low-power enhanced) process. Kilopass' XPM family provides up to 1Mb of storage capacity for portable device SoCs (System on Chip) that need the lower standby power consumption the IBM 65nm 10LPe process provides. Kilopass has successfully completed 1000 hours of High Temperature Operating Life (HTOL) and 1000 hours of High Temperature Storage Life (HTSL) per JEDEC 47 standard qualification on the IBM 65nm 10LPe process with no failures, thus assuring designers of at least 10 years of operating life for the XPM NVM.

Front End Design Summit at Cadence

Cadence is hosting a Front End Design Summit on Thursday, December 6, 2012. The all day workshop which following the tradition of Silicon Valley will start at 9:30am to give time for everyone to battle the traffic, will end at 5:00pm. The workshop will be held in Building 10 at the Cadence campus, 2655 Seely Avenue in San Jose.

Gray Cells In Your FPGA

Shakeel Jeeawoody, VP of Marketing at Blue Pearl Software, published a paper that describes a technique developed by his company to significantly improve the inter block analysis for complex designs. The technique is called Grey Cell Methodology.

Synopsys and Tektronix Offer New New FPGA-Based Prototyping Solutions

Increasing design complexity is posing heighten verification complexity. Most of the consumer electronic products that are pushing vendors toward state of the art processes require real time responses. These applications cannot be debugged using software based tools. Thus the use of FPGAs for SoC verification has become the norm.

In the last two weeks both Synopsys and Tektronix have introduced new powerful verification solutions to aid engineers developing SoC devices.

Jasper Users Group Is On The Horizon

One of the greatest values of a User Group is the ability to network with other users and compare the methods used with various tools from the vendor. The Jasper Users Group meeting will be held on November 12 and 13 at the Cypress Hotel in Cupertino, CA. The gathering will be especially interesting to designers, verification engineers and engineering managers. Attendees from around the world to share the latest verification best practices.

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