This site is dedicated to the thoughtful analysis of the EDA industry. It will provide editorial pieces about events in the EDA industry that, in our opinion, are significant to developers of electronic systems. More.

Quality EDA Software Does Not Just Happen: It Is Engineered

One of the common characteristics of EDA companies is that most often the engineering teams are managed by hardware engineers. The result is that during product development much attention is paid to the problem to be solved and less emphasis is given to the software development methodology used. This to me is the core message of a presentation given at UC Berkeley by two staff members of Blue Pearl Software.

Calypto PowerPro Adopted by Core Logic for Advanced RTL Power Reduction

Calypto® Design Systems announced that Core Logic Inc., a fabless semiconductor manufacturer, has adopted PowerPro CG as their primary power optimization tool for designing their complex system-on-chip (SoC) products.

Synopsys vs. Mentor: Is Cadence Paying Attention?

In a strange twist of reality I learned of the proposed acquisition of EVE by Synopsys because of a legal maneuver by Synopsys. It is not possible for a party to sue another party unless the first party has a material reason for the legal action. Thus the fact that Synopsys filed a Complaint for Declaratory and Injunctive Relief against Mentor Graphics on the subject of the legal proceedings that Mentor initiated months ago against EVE is an indication that Synopsys now would be materially damaged by the legal battle in the emulation business.

Zuken Blogs About Its Participation In The 20th FED Conference

A just published blog that you can read in its entirety by clicking on the Zuken logo on the right, describes Zuken's role at the 20th FED conference in Dresden, Germany. The conference is a major PCB event in Europe.

In addition to its presence on the exposition floor, Zuken employees presented two papers during the technical session. Masoud Raeisi discussed design rules violations PCB designers often make, while Ralf Bruening covered design challenges of PCI-Express.

DeepChip Results of Synopsys Acquisition of Springsoft Not Surprising

When John Cooley reported the results of his survey on the Springsoft acquisition by Synopsys, the results followed the trend. An impressive 78% of the respondents saw the acquisition as been bad. Not that this would change Synopsys mind, of course. And I am sure that most of these respondents will swallow their opinions and purchase the licenses from those they love to hate: the Synopsys sales force.

Jasper User Group Meeting 2012

Jasper design Automation will hold its 2012 Users Group meeting at the Cypress Hotel in Cupertino on November 12 and 13. Jasper’s annual user meeting will gather designers, verification engineers and engineering managers from around the world to share the latest verification best practices. Jasper’s User Group meeting is an interactive, in-depth technical conference, which focuses on the needs of the Jasper Design Automation user community with the primary goal being to deliver immediately useful technical content.

A Practical Approach to Chip-level Assertion-Based Verification

Mitsuhiro Matsumoto, EVE KK

Are you using assertions in your logic verification?

Assertion-based verification is rapidly gaining popularity as a methodology for more efficient SoC debugging. Both HDL simulators and property-based formal verification tools are recognized as assertion-based verification platforms.

Cadence Releases OrCAD 16.6, Boosts PSpice Performance

I must confess that this announcement came as a surprise. Coupled with the introduction of a new version of Allegro that I covered yesterday, Cadence Design Systems has launched the Cadence® OrCAD 16.6 PCB design solution with new features, enhanced customization capabilities, and 20 percent simulation performance improvements that provide customers a shorter, more predictable path to product creation. Additionally, a new signal-integrity flow introduces a higher level of automation that gives usability and productivity benefits for circuit simulation of performance-driven digital circuits requiring pre-layout topology and constraint exploration and development for high-speed design. The Cadence OrCAD 16.6 PCB technology is scheduled to be available in Q4 2012.

Join us in the global movement at Zuken Innovation World

by Dionne Hayman

This year we’re doing our annual conferences on a GRAND scale. Last year you might have been familiar with Z-DAC in North America, Innovation Fair in Japan, or Engineering Days in Europe. This year, we’ve brought them all together and centered on a consistent theme for all of our global conferences – Innovation.

In 2012, no matter where you’re based, your local annual conference will be the much the same as what your counterparts experience on the other side of the world. The content differs slightly to cater for specific local interests, but the approach is the same.
The emphasis of the conference is networking, learning and sharing innovative ideas.

Cadence Allegro Uses Microsoft SharePoint

Cadence Design Systems, Inc. has announced Allegro 16.6 that it claims will accelerate timing closure for high-speed interfaces by 30-50 percent, through timing-aware physical implementation and verification delivered in the industry’s first ECAD team collaboration environment for PCB design using Microsoft® SharePoint® technology. The Allegro release 16.6 PCB solutions will be available in Q4, 2012

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