This site is dedicated to the thoughtful analysis of the EDA industry. It will provide editorial pieces about events in the EDA industry that, in our opinion, are significant to developers of electronic systems. More.

Arrogance On Display –- Or Is It Naiveté?

As reported by Michael Santarini in:

Cadence creates uproar leading into DAC

Technology Needs Business Acumen for Success

Bernie Aronson is a colorful yet no-nonsense guy – a leader that has contributed to the growth of the EDA industry. Bernie possesses both technical and financial knowledge, a characteristic too often lacking in CEO’s of EDA companies.

Synopsys Interoperability Forum

May 17, 2005, Santa Clara—Alireza Kasnavi, R&D manager for Synopsys presented a technical update to the Composite Current Source (CCS) models for timing analysis here at the 17th Synopsys interoperability forum. This set of models is becoming necessary in designs migrating to 90 nm and smaller process nodes as former secondary effects are growing in significance and consequence.

Mentor offers a standard for verification

The announcement by Mentor Graphics of the release of the Questa 6.2 verification platform included a new technology module called Advanced Verification Methodology or AVM. The AVM is an open, non-proprietary verification methodology, implemented in Both SystemC and SystemVerilog, that supports a true system-level-through-RTL design and verification flow. In contrast to other verification platforms on the market, AVM is independent of any other proprietary products and thus can be used with verification products from other EDA vendors.

The devil is in the numbers

My previous article on the 2005 financial results of the EDA industry as reported by the EDAC Market Statistics Service (MSS) looked at EDA revenues at the macro level, as they relate to the electronics industry financial performance. If you missed it you can read it here.

Economic forces, not capriciousness determine EDA revenues

On April 6 the EDA Consortium (EDAC) announced the results for 2005 of its Market Statistics Service (MSS). Superficially the results provide more fuel to the pundits who have, especially of late, found that all was wrong in EDA. A closer look at the data results yields a more positive judgment of the industry.

Keating acts as a real user

Michael Keating, Synopsys fellow and author of the Reuse Methodology Manual, delivered a talk on "Simplicity and executability: cornerstones of quality" at the International Symposium on Quality Electronic Design.

MIT professor advocates going multi-core in designs

Multicore Expo Santa Clara, March 21, 2006 -- CA Anant Agarwal, professor at MIT, discussed "Going Multi-core: Opportunities, Challenges and Dreams" in his keynote talk. After noting that processing demands are outstripping available compute capabilities, he gave the example of a board-level product with 1 CPU, 20 DSP chips, 16 FPGAs and an ASIC.

Mentor Graphics Brings Process Variability Data into the Design Flow

A couple of years ago, in the pages of EDN, I spoke about the need to create an integrated team among system houses, masks makers, and foundries in order to achieve acceptable yields on products manufactured with processes below 90 nm in feature size. Last week Mentor Graphics Corporation announced availability of the Calibre(R) LFD(TM) (Litho-Friendly Design) product, signaling a major rethinking of the IC design creation flow, and expanding the design for manufacturing (DFM) solutions from Mentor.

Novas adds Alexander Siloti to its orchestra

Novas Software, Inc announced its new family of Silotiâ„¢ Visibility Enhancement (VE) products to address the problem of decreasing visibility into the functional operation of complex ICs during late stage verification and system validation. In early simulation runs, engineers achieve full visibility by dumping as many signals as needed. But in full-chip regression simulation, the number of signals is so large that dumping everything becomes prohibitively expensive, and users must be selective.

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