Physical Design

TSMC Validates Cadence 3D-IC Technology for Its CoWoS(TM) Reference Flow

Last week I wrote that TSMC had validated Synopsys' design flow on its 3D-IC process. Today I received a press release from Cadence stating fundamentally the same thing with regard to its design flow. It is clear that work on 20 nm processes is intensifying as a way to justify the significant investment required by system companies to use it.

Synopsys and TSMC Deliver 3D-IC Design Support

May be you think the 3D-IC pace of development is too slow, but I am of the opposite point of view. Synopsys announced that it is delivering a comprehensive 3D-IC design solution that is included in TSMC's CoWoS™ (Chip on Wafer on Substrate) Reference Flow.

Springsoft Releases Laker³ And A New Analog Prototyping Tool

The Laker custom IC design platform may not be the first layout tool an engineer would name, but it has continued to gain market shares since its introduction and now counts leading semiconductors companies as its customers. SpringSoft, Inc. has made a considerable step toward increasing its market share with the release of its Laker3 custom IC design platform and the new Laker Analog Prototyping tool. The third generation of the Laker product family delivers a complete OpenAccess (OA) environment for analog, mixed-signal, and custom digital design and layout that is optimized for performance and interoperability in 28 and 20-nanometer (nm) flows. Laker customers with current maintenance contracts can upgrade immediately at no charge. The new Laker Analog Prototyping tool is list priced starting at US$80,000 per year for a three-year subscription license.

Docea Power Provides Solution to Power Issues

Although design using 65nm processes began to notice that power use and distribution were becoming a critical aspect of design, the 40nm process node is the critical boundary. This process and all others that follow it, use geometries that are significantly sensitive to power levels, transitions between levels, and the use of multiple power trees in the design.

There are two important reasons for engineers to concern themselves with how much power a design consumes. The proliferation of portable devices has highlighted how much we still do not know about batteries. Extending the executable life of a device between recharging the battery is a highly competitive advantage in the portable communication and computing markets. The second is heat. In the early days of laptops, I remember devices that were uncomfortable to use due to the heat dissipated. These computers were table tops, not laptops, unless one had an unusually high tolerance for pain.

Cadence Accelerates High-Performance, Giga-Scale, 20nm Design With Next-Generation Encounter RTL-to-GDSII Flow

Cadence Design Systems, Inc. afew days ago has introduced the latest release of Cadence Encounter RTL-to-GDSII flow for high-performance and giga-scale designs, including those at the latest technology node, 20 nanometers. Developed in close collaboration with leading IP and foundry partners and customers, the new RTL-to-GDSII design, implementation, and signoff flow enables more efficient development of SoCs, meeting and exceeding the power, performance and area demands of today's market requirements.

Mentor Introduces An Integrated Solution for Component-to-System Thermal Characterization and Analysis

Designers working on subsystems and systems using information for LED, semiconductor, and package components use complex thermal analysis software to help accelerate the design of their products but the analysis, typically based on vendor datasheets, often provides insufficient results. Clear, accessible, and reliable data relating to thermal characteristics upstream and downstream is critical. Methods to achieve this have traditionally been awkward, manual and therefore error-prone.

Springsoft Laker Blitz Targets Chip Finishing Applications

SpringSoft, Inc. has focused its attention of a portion of IC development that is generally performed using traditional place and route tools that have long execution time. Chip finishing very often requires local modifications to the layout, yet, using the tool required for a full place and route job means that much unnecessary work is performed. This leads to a waste of time since designers need to wait many hours, often up to half a day, to see the results.

Springsoft Targets Chip Finishing Applications With Laker Blitz

Laker Blitz is a chip-level layout editor that is specifically optimized for speed and user productivity during the chip finishing stage of the IC/SoC design process. It loads and exports GDSII data files 5 to 20 times faster than conventional layout tools and offers more robust layout editing capabilities than most high-capacity layout viewers.

Laker Blitz targets a variety of chip finishing applications, including IP merging, SoC assembly, and chip-level DRC reviews, that are routinely performed by semiconductor manufacturers, foundries and fabless design companies.

Magma Delivers A New Version Of Titan AMS

Magma Design Automation announced the availability of a new release of the Titan Analog/Mixed-Signal (Titan AMS) Design Platform. With patent-pending analog design technology, Titan provides an innovative FlexCell-to-GDSII analog/mixed-signal (AMS) flow that organically integrates both electrical design and physical design into one unified design methodology. More than 30 customers, including the majority of the top 20 semiconductor companies in the world have adopted Titan AMS, according to Magma.

Mentor Graphics and JEOL to Develop Advanced IC Mask Writing Solutions

As I said a number of times, advanced process technology demands a close cooperation among all parties necessary to successfully transform a product idea into a profitable product. Thus at the tail end of the development process companies that offer mask making equipment and EDA vendors that provide the tools for producing the required patterns must work together to find an efficient compromise that lowers costs.