Last week I attended the Common Platform Technology Forum. The members of the Common Platform, IBM, Samsung, and Globalfoundries organized the event to market both their 32/28 nm foundry capabilities and the work they are undertaking in developing their 20 nm process.
Dr. Stephen Woo of Samsung, not surprisingly sees development being fueled by consumer devices like smartphones enabling the mobile office, infotainment including smart TV sets, and a connected society that would also make heavy use of tablet PC's.
The challenges to the realization of such devices are: delivering high performance while using low power, miniaturization and integration that requires advanced packaging, and the cost of R&D to solve these problems and, more importantly, develop process recipes.
The high cost of R&D for process development was a common theme, repeated also by Dr. Chia Song Hwee from Globalfoundries, and Dr. Gary Patton from IBM. Dr. Patton stated that the current 32/28 nm process had been in development for the last ten years, and it was imperative for any future development to be done in partnerships and with a long term focus.
The Common Platform Alliance has chosen High K Metal Gate (HK/MG) as the nucleus of the process for 32 nm and has also defined the 28 nm process as an optical shrink from 32 nm thus saving both time and money from developing more complex migration paths.
But 20 nm is a very different story. To begin with Dr. Patton surprised the audience by stating that this new process will implement the "gate last" method, contrary to the 32/28 nm process which uses a "gate first" method. And this even after he showed a table that clearly displayed that the "gate first" method was superior to the one chosen. Dr. Patton was very careful to avoid any specific reason for the choice aside from stating that "it works better".
The Common Platform members all see the need to become providers of qualified IP. That does not mean that they want to develop the IP internally, only that they must be the ones qualifying and distributing the IP. I understand the message as being: we want a piece of the profits.
On the subject of cost, all the speakers justified the Common Platform Alliance in terms of capabilities and cost reduction, but also said that even their joint assets were not sufficient to achieve a timely and successful implementation of the next process node. For that reason the Alliance has created another group of companies, called the Joint Development Alliance whose members are: Infineon, Renesas, STMicroelectronics, and Toshiba. They work closely with the Common Platform members as partners in the development. Note the absence of any EDA input within the companies constituting the two inner circles.
The third layer of "contributors" does include Cadence, Magma, Mentor, and Synopsys, with Magma receiving less presence at the Technology Forum (was it because they were not Platinum sponsors?). ARM is also a member of the same layer of collaborators as the EDA vendors, mostly thanks to its willingness to allow the Alliance to use their cores as test circuits.
I find it very interesting that ARM, Cadence, Mentor, and Synopsys were all Platinum sponsors of the Forum. They are certainly very welcome contributors of funds, or may be they are allowed to pay for the privilege of being associated with the Common Platform. They certainly do not seem to be required in the highly complex research and development to produce a new process. May be it is taken for granted that they will be able to develop the required CAD capabilities in time and with a realistic price. After all haven't they done exactly that until now?
Although I have much respect for semiconductor companies, after all I started my career in a microelectronics laboratory, I find their approach to EDA ill advised. EDA is taken for granted, and made to pay in order to play. The contribution of EDA technologists appear to be an afterthought, once the process is developed. It is assumed that there will exist appropriate EDA tools to support it. The statement was made that given the complexity of the 20 nm process everything after a GDSII file was the province of the foundry: no peeking or tweaking allowed.
Will we get to the point where CAD tools will have to be personalized to the foundry of choice? Porting a product to another foundry process, a common practice called second sourcing, was described as being equivalent to developing a different design at 20 nm. Traditional second sourcing, said Dr. Patton just cannot be done.